Linux Kernel Thanks Panou. We aren’t using petalinux, but the kernel config stuff all looks the same. Note that it attaches a Generic PHY driver to eth1, and the phy id is: I’ll update you when I have more information. I had seen that, but we run both PHYs a 1.

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Note that it assigns a different MAC address than is assinged in the device tree file.

net: phy: marvell: fix Marvell 88E1512 used in SGMII mode [Linux 4.9.36]

Check the reset pin to the PHYs. This seems to make sense, as all the other dual phy configurations I see have PHY addresses that aren’t zero. I don’t have the Marvell datasheet handy, but recall seeing that when run a 1. We are not able to run our dual GEM config. We have tried to apply the patch, but does’nt works Note that it attaches a Generic PHY driver to eth1, and the phy id is: When we get back to the issue Marvelll will post whatever resolution we come up with.

Note that I am using two different sub-nets – the With linux this indeed ,inux a problem, when doing it correctly in devicetree then lots of errors come during boot, claiming PHY 0 is invalid, then PHY 0 is enabled, and working, and the second PHY with address 1 valid address remains not configured and is fully not accessible. Yes, I have tried it, but eth1 still doesn’t work.


We verified that before trying it in the kernel. I’ve tried your device tree example as well as different examples found:.

net: phy: marvell: fix Marvell 88E used in SGMII mode – Patchwork

We aren’t using petalinux, but the kernel config stuff all looks the same. It’s likely that a hardware workaround in the fabric is easier to implement ljnux digging into the Linux core software. Thanks for the information.

Linux Kernel Thanks Panou. We have detected your current browser version is not the latest one. The device tree in the newer kernels uses marvel MACB drivers.

There was a little communication confusion with Xilinx. Give Kudos to a post which you think is helpful and reply oriented. Could you explain how to implement Xilinx provided patch marvelp each these different steps? All forum topics Previous Topic Next Topic.

I tried it without success.

Not sure about the dsa or link. Patch is applicable ONLY to the So I would suggest you to try testing the setup in We are running a single Marvell 88e on a custom board, and it refuses to work at all.


Solved: Dual Marvell 88e PHY Ethernet problem – Xilinx – Community Forums

I haven’t used Zynq before, so maybe this suggestion is not appropriate. FYI, the patch is here, but not applicable to any of the current Xilinx kernel releases: Copyright c – Intel Corporation.

I have verified that I can read the OUI bits from the PHY registers using u-boot mdio read 0 2, mdio read 1 2 – other addresses do not respond. Hoping to get a pre-release of the However, eth1 still doesn’t work correctly. Please upgrade to a Xilinx. If they both operate at 2.